Dear everybody Using the code of the CRC32 exists within the ethmac core I tried to test it separately by verifying it's result with the result from obtained from the calculator of http://www.zorc.breitbandkatze.de/crc.html for example: using this calculator for a Data message=U (which is 8'h55) we will get CRC=C9034AF6 to check my work I made this testbench // eb1 1 always @(posedge Clk) begin Data = 4'b0101; if (Crc[31:0] == 32'hc9034af6) begin $display("the CRC is given after", Clk_Counter," clocks"); #5 $finish; end end when running the simulator and make a break point at the $display line I found it doesn't stop and continue running forever Do you think there is a mistake with my work? Do you think the result of this calculator is not right? I appreciate ur help Thanks Mohammad

Hi Mohammad, Seem my comments below. m.abdulmoniem at gmail.com wrote: When setting the breakpoint at the $display line, it depends on the if condition whether it will be reached or not. You should rather set it on the if-statement line. Also, you should not put the $finish statement inside a condition, because you want the simulation to finish no matter whether it passed or not. Then, although I am not familiar with the block you are using, you are sending data into the block and expect the result to be there right away. You should at least wait one time step and then check the result. But rather look in the specification of the block and see what the timing constraints are and how long you have to wait for the result. And finally, make sure you are checking the correct values. With CRC there are other things one can make wrong, despite having the right polynomial. I remember seeing some discussions about this on comp.arch.fpga or any of the vhdl or verilog newsgroups. If you do a search on http://groups.google.com you might find some useful posts. In one post I remember someone provided the data for setup, testvector and expected output for a CRC32. Hope that helps. Cheers, Guenter